Latches
T Latch with Reset
Description When the Reset is Disabled and the Toggle is LOW, the Clock has no effect on the Output.

When the Reset is Disabled and the Toggle is HIGH, the Clock will toggle the Output with each rising edge of the Clock.

When the Reset is Enabled, the Output will be forced LOW. If the Reset is subsequently Disabled, there will not be an update to the Output until the next rising edge of the Clock.

The Output is not persistent when powered-down.
Availability
  • Available only in the dw2xx & dw2xx-v2 series products
  • Requires library: Process Control (option -05)
  • Firmware versions 0x2007 and later
savvy-SFD Graphic trLatch
Graphic with Parameters trLatch

Parameters

Toggle Input, Read-write, Boolean (signed 16-bit integer)
0 = Low
1 = High
Clock Input, Read-write, Boolean (signed 16-bit integer)
0 = Low
1 = High
Reset Input, Read-write, Boolean (signed 16-bit integer)
0 = Inactive
1 = Reset
Output Output, Read-only, Set to default on hard initialization, Boolean (signed 16-bit integer)
0 = Low
1 = High